Approaches to Trim OR1200

OR1200 Module Level Utilization:
1954 Slices, initial slice utilization for or1200_top


After removing CUST5 instruction from or1200_alu:
1873 slices, (1954-1873)/1873 = 4.32% area improvement.


After modifying "SHIFT and ROTATE" logic of or1200_alu:
1839 slices, (1954-1839)/1839 = 6.25% area improvement

Customize minsoc as an OpenRISC sub-system

GOAL
To create a SoC sub-system based on minsoc and OpenRISC

STEPS

1. obtain minsoc and OpenRISC from SVN repository
   

   $ (origin) svn co http://opencores.org/ocsvn/minsoc/minsoc/trunk minsoc
   $ (subsoc) git clone git://github.com/artek/minsoc.git minsoc
   $ svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk openrisc
   

2. follow steps for "GNU tool chain with newlib"
   
   1. build and install or1ksim
      

      edit /etc/ld.so.conf.d/or32.conf, and add /opt/or1ksim/lib

   2. install required library (MFP, MPFR) for building toolchain
      

      $ sudo apt-get install libgmp3-dev libmpfr-dev dejagnu expectk

   3. build toolchain with newlib
      

      $ cd openrisc/gnu-src
      $ sudo ./bld.sh --prefix /opt/or32-elf-new --or1ksim /opt/or1ksim --force
      

   4. add or32-gcc and or1ksim binary to $PATH
      

      export PATH=${PATH}:/opt/or32-elf/bin:/opt/or1ksim/bin

3. refer to "Howto: Porting Newlib" to bring up your own BSP
   
   • config new target as "NON-REENTRANT", "NOT NAMESPACE CLEAN" to reduce generated code size
   • config new target with "-DSMALL_MEMORY" to reduce page size from 4KB to 128B for malloc
   • edit configure.host:
     

     or32-*-*)
     # syscall_dir=syscalls
     newlib_cflags="${newlib_cflags} -DMISSING_SYSCALL_NAMES -DSMALL_MEMORY"
     ;;

   • 
     
4. follow the minsoc-HOWTO for simulation
   evince minsoc/doc/howto.pdf
5. FPGA Impmentation
   
   1. add minsoc_sub to your toplevel
   2. update "Verilog Include Directories" for minsoc to Synthesis options of ISE
      

      ../../rtl/minsoc/rtl/verilog/ (for minsoc)
      |../../rtl/minsoc/rtl/verilog/or1200/rtl/verilog/ (for or1200)
      |../../rtl/minsoc/rtl/verilog/uart16550/rtl/verilog/ (for uart16550)

1. check out openrisc repository from opencores
   svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk openrisc
2. build up toolchain
   cd toolchain_install_scripts/
   
   1. sudo ./crossbuild.sh
      build or32 toolchain and install it to /usr/local/
   2. sh MOF_ORSOC_TCHN_v5c_or32-elf.sh
      build toolchain and or1ksim to specified path
3. 
   

CONS

• or32 ld does not support --gc-sections
  

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